1. Field of the Invention
This invention relates to a computation circuit such as, for example, a semiconductor processor. More specifically, this invention relates to a technique for extending the dynamic range of a computation circuit.
2. Description of the Related Art
Computation circuits include, for example, semiconductor processors. And, DSPs (digital signal processors), for example, are known as types of semiconductor processors. In general, computation circuits use computation units, data buses, memory and similar to perform data computation. When computations are performed, data is sent from memory to the computation unit via a data bus; and, computation results are sent to the memory or elsewhere via a data bus.
Many computation circuits comprise functions to perform accumulation. Accumulation is computation of the sum of numerous data items. When accumulation is performed, the computation unit reads one data item at a time from memory via a data bus, and adds the data items in succession. Accumulation processes are adopted in a controlled algorithm used in, for example, state evaluators and Kalman filters.
When performing accumulation, computation circuit overflow may occur. Overflow is the increase of the bit width of the computation result beyond the dynamic range. For example, when the dynamic range of a computation circuit is 16 bits, the values that can be processed by this circuit are from “215−1” to “−215”. Hence when the computation result is larger than the maximum positive value “215−1” or smaller than the maximum negative number “−215”, overflow occurs.
In order to suppress the occurrence of overflow, some method may be used to extend the dynamic range. In Japanese Patent Laid-open No. 2000-35875, a technique is disclosed for extending the dynamic range without extending the bit width of the computation unit, data bus or similar. By means of this technique, an up/down counter is used as an overflow counter. This up/down counter is counted up when a positive overflow of computation results occurs, and is counted down when a negative overflow of computation results occurs. And, when all computations are completed, if the overflow counter value is positive, the computation circuit outputs the maximum positive value as the computation result. On the other hand, if the value of the overflow counter is negative when all computations are completed, the computation circuit outputs the maximum negative value as the computation result. Extension of the dynamic range without extending the bit width of the computation unit, data bus or similar is extremely useful. This is because if the bit width of the computation unit, data bus or similar is extended, the instructions and codes used by the computation circuit must all be modified.
As described above, the device of Japanese Patent Laid-open No. 2000-35875 outputs the maximum positive value or the maximum negative value of the computation unit when an overflow occurs in the final result of accumulation. However, when there is an overflow in the computation result, the accurate computation result cannot be obtained. Hence The count value of the overflow counter cannot be adopted without modification as the upper bit, that is, the extended bit. This is because when there is an overflow of the computation result, the count value of the overflow counter does not necessarily accurately represent the upper bit of the computation result.
In addition, the device of Japanese Patent Laid-open No. 2000-35875 does not take into consideration cases in which a plurality of independent accumulations are executed in parallel. For example, when performing accumulation of complex numbers, there is a need to perform accumulation of real numbers and accumulation of imaginary numbers in alternation.